SRAM, as a typical type of memory, has advantages including high speed, low power consumption, and standard process compatibility, etc. The SRAM is widely used in computers, personal communication devices, and consumer electronics (intelligent cards, digital cameras, or multiple media players, etc.), etc.
With the continuous development of semiconductor technology, the technical node has become smaller and smaller, and multiple-gate devices have attracted more and more attentions. Fin field-effect transistors (FinFETs) are a common type of multiple-gate devices which has been widely used in the SRAMs. FinFETs are able to effectively enhance the performance of SRAMs.
A SRAM unit often includes two pull-up (PU) transistors, two pull-down (PD) transistors, and two pass-gate (PG) transistors. The two PU transistors are two PMOS transistors. The two PD transistors are NMOS transistors. The two PG transistors are also two NMOS transistors.
For high quality SRAMs, the PD transistors, the PU transistors and the PG transistors may need different drive currents, such as read current (Iread), or stand-by current (Isby), etc., to match the performance requirements. The drive current of a FinFET is proportional to the area of its channel region. Thus, the drive current of the FinFET is able to be adjusted by varying the area of the channel region. In existing techniques, the fin size and the gate size of the FinFETs in a SRAM unit are the same. Thus, the FinFETs having single fins have a same channel area. Therefore, in order to increase the drive currents of the FinFETs, it requires the FinFETs to have multiple fins.
Currently, according to the performance requirements of different SRAMs, the PU transistors, the PD transistors and the PG transistors need different numbers of fins, respectively. Thus, in the cell layout design, the fin frames are different for different SRAM cells; and the cells with different sizes have to be designed separately.
However, according to the present disclosure, such cell layout designs have a plurality of issues. First, the cell layouts of different structures (source, drain, and gate, etc.) cannot be shared. Further, it requires different periphery circuits for different structures. Further, it is relatively complex to change the masks with different cell layouts for different structures during the fabrication process. Further, more mask area may be needed because the areas of the cells are different. Therefore, the research and development cost of SRAMs are relatively high. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.